1. Field of the Invention
The present invention relates to code division, multiple access (CDMA) communication systems, and, more particularly, to scheduling correlation operations of a shared, vector correlator of a CDMA receiver.
2. Description of the Related Art
Several code division, multiple-access (CDMA) standards have been proposed, and one such standard is the IS-95 standard adopted for cellular telephony. As with many CDMA systems, IS-95 employs both a pilot channel for a base station and data, or message, channels for communication by the base station and users. The base station and users communicating with the base station each employ assigned, pseudo-random sequences, also known as pseudo-noise (PN) code sequences, for spread-spectrum xe2x80x9cspreadingxe2x80x9d of the channels. The assigned PN code sequence is a sequence of a predetermined number of bits. For each user transceiver, the PN code sequence is used to spread data transmitted by the transceiver and to despread data received by the transceiver. The PN code sequence is used for both In-phase (I) and Quadrature-phase (Q) channels, is a sequence with a known number of bits, and is transmitted at a predetermined clock rate.
Each bit-period, or phase transition, of the PN code sequence is defined as a chip, which is a fraction of the bit-period of each data symbol. Consequently, the PN code sequence is combined with the data sequence so as to xe2x80x9cspreadxe2x80x9d the frequency spectrum of the data over a larger frequency spectrum. In IS-95, for example, 64 chips represent one data symbol. The pilot channel and each user are also assigned a different Walsh code that is combined with the spread channel to make each spread channel signal orthogonal. The pilot channel is assigned the all zeros Walsh code. An exclusive-OR combination of the zero Walsh code with the PN code sequence of the I and Q channels, respectively, leaves the PN code sequence of the pilot channel unaltered. No data symbols are spread or transmitted on the pilot channel.
To determine when a signal is transmitted, and to synchronize reception and processing of a transmitted signal, IS-95 specifies a correlation finger correlating a known portion of the PN code sequence, for example, an IS-95 pilot epoch, with the sampled received signal. The pilot epoch is the time interval over which a pseudo-noise (PN) code sequence of a pilot signal repeats. The known portion of the IS-95 pilot epoch is the first 64 chips output from I-phase and Q-phase PN sequence generators subsequent to a rollover state. The beginning of the pilot epoch is the rollover state, and is the state at which the I-phase sequence and Q-phase sequence in respective PN generators have the same logic value in all register stages of the PN code generator. The IS-95 system may insert an extra value in the PN code sequence so that the PN code sequence is a multiple of 2. Additional logic may be required to insert the extra value into each sequence following 14 consecutive 1""s or 0""s. The extra value renders a 215 chip period PN sequence. Consequently, for systems such as IS-95, at the beginning of the pilot epoch the value in the first register stage is forced to a logic xe2x80x9c1xe2x80x9d prior to the next state transition from the all zero register state.
Demodulation of a spread signal received from a communication channel requires synchronization of a locally generated version of the PN code sequence with the embedded PN code sequence in the spread signal. Then, the synchronized, locally generated PN code sequence is correlated against the received signal and the cross-correlation extracted between the two. For a user channel, the signal of the extracted cross-correlation is the despread data signal. For IS-95 systems, demodulation begins by first synchronizing a local code sequence pair, one for the I-phase spread data channel (I-channel) and one for the Q-phase spread data channel (Q-channel), with an identical pair of PN code sequences embedded in the signal received from the communication channel.
Communication systems are often subject to transmission path distortion in which portions, or paths, of a transmitted signal arrive at a receiver, each portion having different time offsets and/or carrier phase rotation. Consequently, the transmitted signal appears as a multiplicity of received signals, each having variations in parameters relative to the transmitted signal, such as different delays, gains and phases. Relative motion between a transmitter and receiver further contribute to variations in the received signal. The receiver desirably reconstructs the transmitted signal from the multiplicity of received signals.
A type of receiver particularly well suited for reception of multipath, spread-spectrum signals is a RAKE receiver. The RAKE receiver comprises several correlation fingers to cross correlate each multipath signal with an offset version of the reference PN code sequence. The RAKE receiver optimally combines the multipath signals received from the various paths to provide an extracted cross-correlated signal with high signal-to-noise ratio (SNR). The RAKE receiver may be analogized to a matched-filter where the path gains of each correlation finger, like the taps of a matched-filter, may be estimated to accurately detect a received multipath, spread-spectrum signal. Since a transmitted signal is subject to many types of distortion as it passes through a communication channel to a receiver (i.e., multipath effects, Rayleigh fading, and Doppler shifts), the receiver must estimate the path gains utilizing the transmitted signal as distorted at the receiver. Thus, the detected received signal will only be as robust as the path gain estimation of each correlation finger in the RAKE receiver.
U.S. Pat. Nos. 5,448,600; 5,442,661; 5,442,627; 5,361,276; 5,327,455; 5,305,349; and 5,237,586, the disclosures of which are hereby incorporated by reference, each describe a RAKE receiver. In RAKE receivers, for each fractional chip increment, a correlation with the pilot epoch is performed, which may be represented using the complex conjugate of the expected sequence, xr(n)+xi(n), as                                                         cc              r                        ⁡                          (              n              )                                =                                                    ∑                                  m                  =                  0                                63                            ⁢                              xe2x80x83                            ⁢                                                                    x                    r                                    ⁡                                      (                    m                    )                                                  ·                                                      y                    r                                    ⁡                                      (                                          m                      +                                              n                        ⁢                                                  xe2x80x83                                                ⁢                        τ                                                              )                                                                        +                                          ∑                                  m                  =                  0                                63                            ⁢                              xe2x80x83                            ⁢                                                                    x                    i                                    ⁡                                      (                    m                    )                                                  ·                                                      y                    i                                    ⁡                                      (                                          m                      +                                              n                        ⁢                                                  xe2x80x83                                                ⁢                        τ                                                              )                                                                                      ⁢                  
                ⁢        and                            (        1        )                                                      cc            i                    ⁡                      (            n            )                          =                                            ∑                              m                =                0                            63                        ⁢                          xe2x80x83                        ⁢                                                            x                  r                                ⁡                                  (                  m                  )                                            ·                                                y                  i                                ⁡                                  (                                      m                    +                                          n                      ⁢                                              xe2x80x83                                            ⁢                      τ                                                        )                                                              -                                    ∑                              m                =                0                            63                        ⁢                          xe2x80x83                        ⁢                                                            x                  i                                ⁡                                  (                  m                  )                                            ·                                                y                  r                                ⁡                                  (                                      m                    +                                          n                      ⁢                                              xe2x80x83                                            ⁢                      τ                                                        )                                                                                        (        2        )            
where:
n and m are integer counters
ccr(n) are the real components of the cross-correlation
cci(n) are the imaginary components of the cross-correlation
y is the sampled received signals
x is the reference sequence (matched-filter PN vector sequence)
xcfx84 is a fractional chip
Thus, as can be seen from equations (1) and (2), four real correlations are performed in the process of performing one complex correlation.
The locally generated PN code sequence (the xe2x80x9creference PN code sequencexe2x80x9d or xe2x80x9creference PN code sequencexe2x80x9d) provides the basic elements for generating reference PN sequences, or matched-filter PN vectors, for matched-filter correlation against the received signal. Each PN code sequence is deterministic with a period of 2Nxe2x88x921 chips (PN values), N an integer greater than 1. The PN code sequence is identical between base-stations in an IS-95 system, and maybe augmented by one chip to provide a sequence with a period of 215 chips. This PN code sequence is also known as the xe2x80x9cshortxe2x80x9d code in IS-95 systems. The PN code sequence of each base-station is used for forward channel spreading, and in IS-95-based CDMA communication systems the code-phase offset of the PN code sequence is unique to a base-station. Therefore, to differentiate between base-stations, each base-station is assigned a unique time offset in the PN code sequence.
A PN code generator of an exemplary IS-95 system provides the code sequence for each of the I and Q channels recursively using a 15th order polynomial, resulting in a period of, for example, 215xe2x88x921 chips. The hardware realization for such a PN code generator is a shift register having 15 stages and with selected shift register outputs combined in modulo-2 addition to form the next PN code sequence value that is also the recursive input value to the beginning of the shift register.
Referring to FIG. 1, there is shown a generalized pseudo-noise (PN) generator 100 as may be used to generate a PN code sequence and a serial correlator 150 that may be employed to correlate a portion of the PN code sequence with a received signal. Such serial correlator may also be employed in a matched-filter vector correlator. The hardware implementation of the PN generator 100 shown in FIG. 1 is of a Fibonacci type, but other types of generators, such as a Galois type, may be used. The generalized PN generator 100 as shown in FIG. 1 includes shift register 102, gain amplifiers 104, and modulo-2 adder 110. PN generator 100 may further include registers 111 and 112 and optional delay 113. In FIG. 1, gain amplifiers 104 have gain values g[n:0], that are the generating polynomial coefficients of the generating polynomial G. Also, S=S[n:0] is the state of shift register 102.
As is known in the art, PN generator 100 generates a code in the following manner. First, shift register 102 is loaded with a polynomial xe2x80x9cseedxe2x80x9d value. The seed value is typically one state of the shift register that forms a portion of the resulting PN sequence. Then, for each clock cycle, the value of the shift register is combined via gain amplifiers 104 in a modulo-2 adder 110. Each gain amplifier 104 adjusts the value in each corresponding stage of the shift register 102 according to generating polynomial coefficients. This is a cyclic process: the value in modulo-2 adder 110 is then applied to the first element of the shift register 102 and the last element is discarded. Each state of the shift register 102 may be loaded into storage registers for use with, for example, the I and Q channels, respectively.
The IS-95 system may augment the PN code sequence by inserting an extra value in the PN code sequence so that the PN code sequence is a multiple of 2. Additional logic (not shown in FIG. 1) inserts the extra value into each sequence following 14 consecutive 1""s or 0""s. The extra value renders a 215 chip period PN sequence. Also, as is known in the art, a periodic bit sequence with a first code-phase may be combined with another sequence to form the same periodic bit sequence with a second code-phase. This process is known as masking. Consequently, a delayed, or offset, version of the sequence may be generated by modulo-2 addition of appropriate state bits of the shift register 102 with a selected mask. Additional logic for correcting the masked sequences may also be required if the PN code sequence is augmented.
Returning to FIG. 1, serial correlator 150 includes delays 151-155, multipliers 161-165, accumulators 171-175 and comparator 180. The delays 151-155 each receive the locally generated PN code sequence from the PN generator 100 and each provide a corresponding PN sequence with code-phase offset of, for example, jzxe2x88x921 chips, j an integer and 1xe2x89xa6jxe2x89xa65. The delay width zxe2x88x921 may be dependent on the type of process using the results of vector correlator 150. For example, zxe2x88x921 may be a quarter-chip width for code tracking, but may be one-chip width for searching. Multipliers 161-165 each multiply the received (sampled) signal x[n] with a corresponding one of the delayed PN code sequences to xe2x80x9cdespreadxe2x80x9d the signal. Accumulators 171-175 each accumulate the result from corresponding ones of multipliers 161-165 for a predetermined period, and comparator 180 compares the results to a predetermined threshold value. Each delay, multiply and accumulate chain may be considered a correlation finger. If the threshold value is exceeded by the result of the correlation finger, then the code-phase of the delayed PN code sequence matches the code-phase of the embedded code sequence in the signal of the correlation finger. The result of more than one correlation finger may exceed the threshold value of the comparator 180 if multipath signal components are present.
For a receiver in a CDMA system using a vector correlator, as would be apparent to one skilled in the art, many matched-filter PN vectors must be generated in a receiver. Each of the search, tracking and demodulation functions is typically performed by a processing unit, each of which employs one or more vector correlator circuits, such as the vector correlator 150 of FIG. 1. For example, in a receiver""s acquisition or search mode the receiver determines whether the pilot signal is present. In acquisition or search mode, the correlation finger must search through all fractional chip offsets of the pilot epoch in order to locate the pilot signal. As described previously, each complex correlation actually requires four real correlations. Correlations of correlation fingers in a RAKE receiver are often performed against multiple, fractional-chip offsets simultaneously, such as during initial search or handoff between base-stations. If a receiver tracks several base stations, as may be required for handoff, then the acquisition mode process must occur for the pilot of each base station.
Further, even when synchronization is achieved when the pilot signal is present, a receiver""s tracking mode must track several correlation fingers, and in the demodulation mode must demodulate a spread user channel. Further, data detection mode detects a signature sequence intended for the particular receiver. The signature sequence, in IS-95, may be a xe2x80x9clongxe2x80x9d PN code sequence for security (i.e., the sequence of the xe2x80x9clongxe2x80x9d PN code is relatively longer than the sequence of the xe2x80x9cshortxe2x80x9d PN code). In the data detection mode, there are several sub-modes. The sub modes include a paging data mode, a synchronization data mode, and a traffic mode, all of which require correlation operations.
RAKE receivers require replication of hardware for each correlation finger performing simultaneous correlation operations, resulting in redundant hardware. Simultaneous correlation operations may be achieved using multiple parallel correlators and vector generators. Prior art methods for generating multiple, matched-filter PN vectors include either generating multiple, parallel PN code sequences, each with a different offset, or applying a set of parallel masks to a single PN code sequence, each applied mask generating a PN sequence having a different offset. However, where a large degree of flexibility is required for scheduling correlation operations, and many different matched-filter PN vectors are required for a single symbol period, the hardware requirements of these methods are impractical.
Serial correlators of the prior art assemble both an offset local PN code and a receive data sequence that are then provided in parallel to the correlator hardware. The multiplexing rate of a serial correlator is limited by its total latency from the initial multiplication, bit-wise addition and accumulation functions of the correlator. Interdependence of each execution stage in the serial correlator, as well as the chip rate of the spreading sequence, limits this multiplexing rate.
The present invention relates to scheduling at least one correlation finger request of a shared vector correlator. Parameters defining an ID-tag for at least one matched-filter PN vector are determined from finger information of a correlation request, and a slot of a periodic symbol cycle corresponding to a time to generate the matched-filter PN vector is selected based on the finger information of the correlation request. An ID-tag is associated with the slot, and the ID-tag of each slot is provided in accordance with the periodic symbol cycle.
An embodiment of the present invention stores the ID-tag associated with the slot in an address of a memory; and sequentially providing each value of a counter. Each value of the counter corresponds to an address of the memory, and the memory provides the ID-tag stored in the corresponding address of the value of the counter.